1. Technical Field
The present disclosure is directed to system-in-packages (SiP) and methods for forming same.
2. Description of the Related Art
System-in-packages (SiP) include multiple semiconductor dice or chips enclosed in a single package body. The semiconductor chips may be located side by side, such as in 2.5-D packages, or stacked on top of each other, such as in 3-D packages.
The SiP typically includes an interposer that is located between the package substrate and the semiconductor chips. In a 2.5-D package, each of the semiconductor chips is electrically coupled to a first side of the interposer substrate, such as in a flip chip configuration.
Generally described, flip chip technology refers to a process and structure in which electrical contacts, e.g., solder bumps, are placed on a semiconductor chip in contact with contact pads of the chip, forming a ball grid array (BGA) on the face of the chip. The chip is then placed active-side down on the interposer with the solder bumps coupled to interconnects or pillars of the interposer. In a reflow step, the solder bumps are reflowed in a heating step to form a solder joint that adheres the contact pads of the chip to the interconnects or pillars of the interposer.
Typically, the first side of the interposer has high density interconnects for coupling bond pads of the semiconductor chips. Thus, the bumps for connecting the bond pads with the interconnects of the first side of the interposer are quite small, such as about 50 microns.
A second side of the interposer is coupled to a package substrate, which forms an outer surface of the SiP. The second side of the interposer includes interconnects that allow for larger solder bumps, such as about 100 microns, for connection to the package substrate. The total thickness of a typical SiP at this stage is about 300 microns. The package substrate may be further processed to have package bumps, e.g., solder balls, formed thereon for coupling to another substrate or board, such as a printed circuit board.
The process of forming the above-described SiP involves separately processing the first and second side of the interposer at wafer level. Typically, the second side of the interposer is processed first to form metal interconnects, copper pillars on the metal interconnects, and solder bumps over the copper pillars. A dielectric layer is formed over the second side of the interposer and around the copper pillars and solder bump. A carrier substrate is mounted to the dielectric layer. The carrier substrate provides support to the interposer while the first side of the interposer is processed to form metal interconnects and copper pillars.
After the copper pillars have been formed on the first side of the interposer, solder bumps of the semiconductor chips are coupled to the front side copper pillars using flip chip technology as discussed. An underfill step is performed to provide underfill material between the semiconductor chips and the interposer. The underfill material is typically an electrically insulating adhesive that is provided around the solder bumps and pillars that couple the semiconductor chip to the interposer. The underfill material provides further mechanical support for the semiconductor chips.
An encapsulation step is performed to encapsulate the semiconductor chips and the interposer. The carrier substrate and the dielectric layer may then be removed. The interposer-chip assembly is then singulated and coupled to a package substrate using flip chip technology. That is, the solder bumps on the first side of the interposer are placed face down onto the package substrate. Again, an underfill step is performed to provide underfill material between the package substrate and the interposer. An encapsulation step is again performed to encapsulate the interposer and over package substrate. Finally, in view of the process being performed at wafer level, a dicing step is then performed for separating into individual SiPs.
The above process includes repetitive steps, such as the underfill and encapsulation steps. In that regard, the process can be unduly costly and time consuming. Furthermore, mounting and demounting the carrier substrate to the interposer can cause warpage of the interposer.